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AUSTIN, Texas (UPI) — U.S. computer scientists unveiled a new processor that has the potential of performing trillions of calculations per second.

The prototype known as TRIPS — Tera-op, Reliable, Intelligently adaptive Processing System — was designed and built by a team of computer scientists at the University of Texas at Austin.

Professors Stephen Keckler, Doug Burger, Kathryn McKinley and their colleagues spent seven years creating the underlying technology that culminated in the chip.

Burger said TRIPS uses a new class of processing architectures called Explicit Data Graph Execution, or EDGE. Unlike conventional computer architectures that process one instruction at a time, EDGE processes large blocks of information simultaneously.

A TRIPS chip contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. Current high-performance processors are typically designed to sustain a maximum execution rate of four operations p per cycle.

The researchers will unveil a fully functional TRIPS prototype during a public presentation Monday at The University of Texas at Austin.

TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) is a revolutionary new polymorphous microprocessor architecture designed and built by the Department of Computer Sciences at The University of Texas at Austin. For the past seven years the research team, led by Professors Doug Burger, Stephen Keckler and Kathryn McKinley, has been working on the design of the processor, an updated cross-platform compiler and the instruction set architecture needed to run it.

The team’s goal is to produce a scalable architecture that can accelerate industrial, consumer, embedded and scientific workloads, reaching trillions of calculations per second on a single chip. This radical new architecture can produce improved single-thread performance—at greater power efficiencies—than conventional designs. This technology, called Explicit Data Graph Execution (EDGE architectures) offers a flexible alternative to the current industrial direction of providing a greater number of processor cores with each passing generation.

The TRIPS prototype processor is a working system that demonstrates the capabilities of this new EDGE technology. Its architecture is composed of many copies of a small number of replicated tiles, reducing complexity and improving ease of design. Produced with generous support from DARPA, each TRIPS prototype processor contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. The prototype is the first on a roadmap that will lead to ultra-powerful, flexible processors implemented in nanoscale technologies. This technology is expected to have significant impact on the computing industry.